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Add parameter on config file to define the width of the memory transaction ID

Created by: cfuguet

This new parameter in the CVA6 configuration packages defines the width of the transaction ID between the I/Dcaches and the interconnection interface.

It should be defined in global CVA6 packages and not in any specific implementation of a cache to ease the integration of different cache subsystems.

Current default value (before this PR) is 2 bits. I kept this value, then no increase in the area is expected. @JeanRochCoulon, can you review these changes?

Thank you

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