Fix definition of the cache size (data and instructions)

Created by: cfuguet

The cache size is a given number of bytes.

Currently it was computed as a given number of lines but then the width of indexes was bad.

With this fix:

• CVA6ConfigIcacheLines and CVA6ConfigDcacheLines define the total number of lines in the cache.
• The cache size is computed as CVA6Config[ID]cacheLines * number of bytes per line
• The configuration packages were modified to keep the original capacities: 16KB for Icache and 32KB for Dcache.

There is an exception for the cv32a6_ima_sv32_fpga_config_pkg where the capacities are 8KB for both Icache and Dcache.