About the fence instruction

Created by: zhaoxiahust

Hi Guys, I noticed the current fence instruction implementation in Ariane flushes the L1 cache. Based on my understanding of the fence in the memory consistency model, it only needs to prevent the re-ordering of load-store instructions. I understand based on the current Ariane implementation, L1 cache needs to be flushed to remove some false data brought by the re-ordered loads.

However, if I implement the fence instruction by preventing the load-store re-ordering, do I still need to flush the L1 cache or not? Based on the explanation of the fence instruction in the RISC-V manual, my implementation does not need to flush L1. However, I am afraid Ariane implements fence instruction for other reasons except for maintaining the memory-ordering as specified by the RISC-V manual. Any comments about this?

Thanks for your help!

Cheers,