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  1. Nov 20, 2024
  2. Nov 18, 2024
  3. Nov 15, 2024
    • AngelaGonzalezMarino's avatar
      Altera opt 1 (#2592) · 33c5d77b
      AngelaGonzalezMarino authored
      The first optimization for Altera FPGA is to move the instruction queue to LUTRAM. The reason why the optimization previously done for Xilinx is not working, is that in that case asynchronous RAM primitives are used, and Altera does not support asynchronous RAM. Therefore, this optimization consists in using synchronous RAM for the instruction queue and FIFOs inside wt axi adapter.
      
      The main changes to the existing code are:
      
      New RAM module to infer synchronous RAM in altera with independent read and write ports (SyncDpRam_ind_r_w.sv)
      
      Changes inside cva6_fifo_v3 to adapt to the use of synchronous RAM instead of asynchronous:
      
      When the FIFO is not empty, next data is always read and available at the output hiding the reading latency introduced by synchronous RAM (similar to fall-through approach). This is a simplification that is possible because in a FIFO we always know what is the next address to be read.
      
      When data is read right after write, we can’t use the previous method because there is a latency to first write the data in the FIFO, and then to read it. For this reason, in the new design there is an auxiliary register used to hide this latency. This is used only if the FIFO is empty, so we detect when the word written is first word, and keep it in this register. If the next cycle comes a read, the data out is taken from the aux register. Afterwards the data is already available in the RAM and can be read continuously as in the first case.
      
      All this is only used inf FpgaAlteraEn parameter is enabled, otherwise the previous implementation with asynchronous RAM applies (when FpgaEn is set), or the register based implementation (when FpgaEn is not set).
      33c5d77b
  4. Nov 14, 2024
  5. Nov 12, 2024
  6. Nov 07, 2024
  7. Nov 06, 2024
  8. Nov 05, 2024
  9. Nov 04, 2024
  10. Nov 01, 2024
    • Matteo Perotti's avatar
      acc_dispatcher: don't issue instruction from buffer if flushing (#2490) · 9e670f64
      Matteo Perotti authored
      The controller flushes the pipeline and all the unissued instructions in the presence of instructions with side effects (e.g., fence).
      The accelerator dispatcher buffer (now used with the Ara RVV Vector processor) is flushed when this happens and avoids accepting a new instruction in that cycle, but it does not prevent the actual issuing of instructions during a flush cycle.
      This fix avoids the issue during a flush cycle.
      9e670f64
  11. Oct 25, 2024
    • slgth's avatar
      doc: keep documentation in sync with the code (#2558) · ab2283c0
      slgth authored
      Both the ISA and design documentations use some parameters generated from the RTL (ports, parameters).
      As of now, they are committed to the repository and can be out of sync with the code.
      
      This PR removes them from the repository and freshly generates them from the code when building HTML files.
      
      This PR also removes prebuilt HTML files (design & ISA docs) and generates them when building the top-level Read the Docs documentation (make -C docs).
      ab2283c0
  12. Oct 23, 2024
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