- Nov 20, 2024
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AEzzejjari authored
Improving frontend documentation
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AEzzejjari authored
Integrating the modifications to the AXI agent made by CEA
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Valentin Thomazic authored
* cva6 refactor & cleanup to enable tandem reports generation for elf tests such as testelf for simu-gate: 1. merge redundant functions to run directed tests in `cva6.py` (`run_c`, `run_elf`, `run_assembly` -> `run_test`) 2. removed broken and unused functions by the way (`run_c_from_dir`, `run_assembly_from_dir`) * collect sim reports of simu-gate job to display them in the cva6 dashboard :
️ the simu gate job will still fail but the result on the dashboard will be accurate and will allow debugging -
BRH authored
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- Nov 18, 2024
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Valentin Thomazic authored
* Disable tandem on riscv-tests-v testlist * More relevant error message on report tandem script Related issue: #2605
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jean-roch coulon authored
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- Nov 15, 2024
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AngelaGonzalezMarino authored
The first optimization for Altera FPGA is to move the instruction queue to LUTRAM. The reason why the optimization previously done for Xilinx is not working, is that in that case asynchronous RAM primitives are used, and Altera does not support asynchronous RAM. Therefore, this optimization consists in using synchronous RAM for the instruction queue and FIFOs inside wt axi adapter. The main changes to the existing code are: New RAM module to infer synchronous RAM in altera with independent read and write ports (SyncDpRam_ind_r_w.sv) Changes inside cva6_fifo_v3 to adapt to the use of synchronous RAM instead of asynchronous: When the FIFO is not empty, next data is always read and available at the output hiding the reading latency introduced by synchronous RAM (similar to fall-through approach). This is a simplification that is possible because in a FIFO we always know what is the next address to be read. When data is read right after write, we can’t use the previous method because there is a latency to first write the data in the FIFO, and then to read it. For this reason, in the new design there is an auxiliary register used to hide this latency. This is used only if the FIFO is empty, so we detect when the word written is first word, and keep it in this register. If the next cycle comes a read, the data out is taken from the aux register. Afterwards the data is already available in the RAM and can be read continuously as in the first case. All this is only used inf FpgaAlteraEn parameter is enabled, otherwise the previous implementation with asynchronous RAM applies (when FpgaEn is set), or the register based implementation (when FpgaEn is not set).
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- Nov 14, 2024
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Nils Wistoff authored
If Hypervisor extension is enabled, the logic required to properly trap to S mode is currently excluded. Fix this by adjusting the if block.
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jean-roch coulon authored
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- Nov 12, 2024
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Côme authored
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Côme authored
* Fill docs/design/design-manual/source/cva6_issue_stage.adoc * Add variables to docs/design/design-manual/source/design.adoc * Update port doc comments in core/issue_stage.sv, core/issue_read_operands.sv and core/scoreboard.sv
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AngelaGonzalezMarino authored
First step to add FpgaAltera optimization parameter
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AngelaGonzalezMarino authored
Additional fix to #2392
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Valentin Thomazic authored
Add failures checks in `.gitlab-ci/scripts/report_tandem.py`: * catch wrong or missing log directory * catch wrong yaml reports
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jean-roch coulon authored
The simu-gate ci job was broken since a while. This PR fixes it.
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jean-roch coulon authored
This reverts commit 485c382b.
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Nils Wistoff authored
If Hypervisor extension is enabled, the logic required to properly trap to S mode is currently excluded. Fix this by adjusting the if block.
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dependabot[bot] authored
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- Nov 07, 2024
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Côme authored
Expands all glob port maps in the core/ directory of this repository except the core/cache_subsystem/ directory, despite the glob port maps in core/cache_subsystem/miss_handler.sv and core/cache_subsystem/std_nbdcache.sv. Also reorders port maps to keep the same order as port declarations.
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Guillaume Chauvon authored
Set HPDCACHE as default cache for FPGA boot configuration ie. cv32a6_imac_sv32
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Jalali authored
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joncapltd authored
This adds a tutorial on how to customise the example coprocessor with your own instructions and test them.
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- Nov 06, 2024
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Matteo Perotti authored
Fix Ara's exception propagation using correct exception_t data type.
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Zbigniew Chamski authored
ix the dhrystone execution script so that any ISS options accumulated in shell variable DV_OPTS are duly propagated to cva6.py.
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- Nov 05, 2024
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Cesar Fuguet authored
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Riccardo Tedeschi authored
The former kind of signal initialization generates compilation errors using VCS to simulate the design due to multiple drivers driving those signals. Since these signals are handled inside the always_ff block, they can just be reset.
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- Nov 04, 2024
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Valentin Thomazic authored
* refactor gitlab ci & collect full fpga build artifacts * remove fpga log.tail from dashboard
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jean-roch coulon authored
This gate count increase has been added by #2555. The root cause has not been found but the deviation is small, and as it impacts the merge process (the ci is red), I prefer to fix the ci.
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Valentin Thomazic authored
Fix dashboard and label links in README (see #2554 )
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Côme authored
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Côme authored
Update the documentation of cv32a65x to make it superscalar. This first PR only updates the documentation of the frontend and decode stages.
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André Sintzoff authored
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Nils Wistoff authored
For `XLEN = 64`, some tools (e.g. VCS) still elaborate the offset generation block for `XLEN = 32`, throwing an elaboration error (illegal bit access). Fix this by generating the AXI offset in an equivalent, parameter-agnostic and tool-friendly way.
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- Nov 01, 2024
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Matteo Perotti authored
The controller flushes the pipeline and all the unissued instructions in the presence of instructions with side effects (e.g., fence). The accelerator dispatcher buffer (now used with the Ara RVV Vector processor) is flushed when this happens and avoids accepting a new instruction in that cycle, but it does not prevent the actual issuing of instructions during a flush cycle. This fix avoids the issue during a flush cycle.
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- Oct 25, 2024
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slgth authored
Both the ISA and design documentations use some parameters generated from the RTL (ports, parameters). As of now, they are committed to the repository and can be out of sync with the code. This PR removes them from the repository and freshly generates them from the code when building HTML files. This PR also removes prebuilt HTML files (design & ISA docs) and generates them when building the top-level Read the Docs documentation (make -C docs).
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- Oct 23, 2024
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