- Nov 14, 2024
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Eric Ackermann authored
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- Nov 08, 2024
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Eric Ackermann authored
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Eric Ackermann authored
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Eric Ackermann authored
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Eric Ackermann authored
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Eric Ackermann authored
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Eric Ackermann authored
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Eric Ackermann authored
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Eric Ackermann authored
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Eric Ackermann authored
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- Nov 07, 2024
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Côme authored
Expands all glob port maps in the core/ directory of this repository except the core/cache_subsystem/ directory, despite the glob port maps in core/cache_subsystem/miss_handler.sv and core/cache_subsystem/std_nbdcache.sv. Also reorders port maps to keep the same order as port declarations.
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Guillaume Chauvon authored
Set HPDCACHE as default cache for FPGA boot configuration ie. cv32a6_imac_sv32
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Jalali authored
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joncapltd authored
This adds a tutorial on how to customise the example coprocessor with your own instructions and test them.
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- Nov 06, 2024
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Matteo Perotti authored
Fix Ara's exception propagation using correct exception_t data type.
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Zbigniew Chamski authored
ix the dhrystone execution script so that any ISS options accumulated in shell variable DV_OPTS are duly propagated to cva6.py.
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- Nov 05, 2024
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Cesar Fuguet authored
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Riccardo Tedeschi authored
The former kind of signal initialization generates compilation errors using VCS to simulate the design due to multiple drivers driving those signals. Since these signals are handled inside the always_ff block, they can just be reset.
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- Nov 04, 2024
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Valentin Thomazic authored
* refactor gitlab ci & collect full fpga build artifacts * remove fpga log.tail from dashboard
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jean-roch coulon authored
This gate count increase has been added by #2555. The root cause has not been found but the deviation is small, and as it impacts the merge process (the ci is red), I prefer to fix the ci.
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Valentin Thomazic authored
Fix dashboard and label links in README (see #2554 )
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Côme authored
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Côme authored
Update the documentation of cv32a65x to make it superscalar. This first PR only updates the documentation of the frontend and decode stages.
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André Sintzoff authored
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Nils Wistoff authored
For `XLEN = 64`, some tools (e.g. VCS) still elaborate the offset generation block for `XLEN = 32`, throwing an elaboration error (illegal bit access). Fix this by generating the AXI offset in an equivalent, parameter-agnostic and tool-friendly way.
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- Nov 01, 2024
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Matteo Perotti authored
The controller flushes the pipeline and all the unissued instructions in the presence of instructions with side effects (e.g., fence). The accelerator dispatcher buffer (now used with the Ara RVV Vector processor) is flushed when this happens and avoids accepting a new instruction in that cycle, but it does not prevent the actual issuing of instructions during a flush cycle. This fix avoids the issue during a flush cycle.
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- Oct 25, 2024
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slgth authored
Both the ISA and design documentations use some parameters generated from the RTL (ports, parameters). As of now, they are committed to the repository and can be out of sync with the code. This PR removes them from the repository and freshly generates them from the code when building HTML files. This PR also removes prebuilt HTML files (design & ISA docs) and generates them when building the top-level Read the Docs documentation (make -C docs).
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- Oct 23, 2024
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Set BHTEntries=128, cache=WT and scoreboardentries=8, Icache size=16384 to improve Coremark and Dhrystone results
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Create dedicated spike.yaml file for cv32a65x configuration. When another configuration is selected, no spike.yaml is provided to Spike, the default internal Spike configuration is used. When hwconfig is targetedi with cv32a65x as reference, cv32a65x spike.yaml is recopied into hwconfig directory.
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Create dedicated linker scripts for cv32a65x configuration. When another configuration is targeted, the default linker script is used (config/genxxx/linker/link.ld). When hwconfig is targeted, linker scripts are recopied into hwconfig directory. Keep only one unique linker script: link.ldi. Remove test.ld file.
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jean-roch coulon authored
This reverts commit 0877e8e4.
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