Add FPU (squashed)

Created by: CKeilbar

This pull request adds a high-performance FPU for full support for the floating-point F and D RISC-V ISA extensions. The FPU is fully IEEE-754 compliant, supporting all rounding modes, exceptions, and numerical correctness.

FPU correctness was verified using this repository, which contains test vectors for all combinations of floating-point instruction and rounding mode. There are ~60 million test cases in total, the vast majority being drawn from the Berkeley TestFloat program.

On the ZedBoard, including the FPU adds about ~7,500 LUTs, ~3,500 FFs, and 9 DSPs, and reduces the frequency by ~20MHz. This cost is worthwhile for applications using floating-point numbers, as emulating floating-point operations in software has overhead on the order of 100x.

The FPU also supports parameterizable single and double reduced-precision number formats, which trades off numerical accuracy for performance and area.

After this is merged, PR https://github.com/openhwgroup/cva5/pull/16 and https://github.com/openhwgroup/cva5/pull/23 can be closed and accelerators-2023 can be deleted, as the FPU includes the changes from both.

This PR is a retry of https://github.com/openhwgroup/cva5/pull/23, but with a squashed FPU commit history for compliance with the license check.