Fix invalidation address and non power of 2 fifos

Created by: CKeilbar

The first fix addresses L1 cache invalidation in the L2 arbiter. Currently, for each unit connected to the arbiter, the arbiter invalidates each units own current address instead of the address of the arbitrated unit.

Currently the depth of FIFOs are implicitly rounded up to the nearest power of 2. Although the processor currently doesn't contain any FIFOs with a non power of 2 depth, this implicit rounding up can cause problems when extending the processor. This second change makes the FIFO behave as if it has the specified depth. For example, a FIFO with a configured depth of 11 will state that it is full when it contains 11 entries (even if it actually has capacity for 16).