Fixes after running SEC vs cv32e40s with SECURE=0. (!952) · Merge requests · OpenHW Group / backup-20241120 / cv32e40x

Eclipse Webmaster requested to merge github/fork/silabs-oysteink/silabs-oysteink_xs-sec-changes into master Sep 15, 2023

Created by: silabs-oysteink

In PR #498 (closed) on cv32e40s there was a list of required changes to the e40x controller to get to a SEC clean state. This PR addresses two changes to align the two cores. The first bullet below is just a refactor and is SEC clean. The second is not SEC clean, and the reasoning here is that without this change the e40x can kill the pipeline for debug or interrupts before a CSR flush handshake is completed (before the jump to the instruction after the CSR is performed).

Refactored branch_in_ex / branch_taken ex. SEC clean.
Not allowing async debug, interrupts or NMI when csr_flush_ack_q == 1. NOT SEC clean.

Fixes after running SEC vs cv32e40s with SECURE=0.

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