Updates related to PR #680 (!689) · Merge requests · OpenHW Group / backup-20241120 / cv32e40x

Created by: silabs-oysteink

Added SUBMODE field to mtvec - tied to 0 (SEC CLEAN)
CSR accesses to mnxti with immediate bits 0, 2 or 4 set will cause an illegal instruction
Number of implemented bits in mintthresh depend on SMCLIC_INTTHRESHBITS. Unused bits are tied to 1. Implemented bits are left justified. (SEC CLEAN when SMCLIC_INTTHRESHBITS = 8)
mscratchcsw now depend om mstatus.mpp instead of mcause.mpp (SEC CLEAN)
Removed instantiated CSR for read-only mclicbase (not directly relevant to PR 680)

From earlier PR #686 and #687, the legalness of accesses to mscratchcsw[l] are updated to reflect the CLIC spec.

Updates related to PR #680