Changed logic for sequence progress detection

Created by: silabs-oysteink

Swapped the RTL detection logic with the logic used in the SVA file. This is done to avoid a combinatorial loop is using 'seq_valid' to calculate first_op of the IF stage.

First PR of a series to clean up Zc code and in particular handling of first_op and last_op.

SEC not determined at the time of PR (for both ZC_EXT=0 and ZC_EXT=1)