Silabs oysteink wb controller

Created by: silabs-oysteink

This is a draft PR for the new WB-centric controller and associated pipeline changes.

Main changes are:

• Exceptions are propagated to WB stage
• CSR writes happens in WB
• RF has a single write port in WB
• Special instructions are propagated to WB
• All pipeline stages have a 'instr_valid' bit, indicating that it's current instructions is valid. Locally used inside stages to gate off secondary enable signales (like alu_en for instance)
• Controller may kill stages (effectively setting next_stage.instr_valid to zero in the next cycle)

Branches are still taken from EX and jumps from ID.

It is not yet feature complete (missing NMI, debug support and MPU exceptions from the LSU module). The code is not properly cleaned up yet (port connections etc may be remnant from previous implementations).

Also note that the instantiation of the tracer module inside the wrapper has been changed to allow for simulations to run with core-v-verif. The tracer module will either be changed later, or replaced by the RVFI based tracer once we get RVFI implemented with the new controller.

Please review and comment, and I'll incorporate the feedback.