Updates to Zc handling in IF stage

Created by: silabs-oysteink

• No prefetch_ready handshake on tbljmp. Table jumps will either generate a pc_set and kill_if when they reach ID, or they will get killed (which also implies kill_if and a new pc_set).
• Sequencer will not get valid_i on trigger matches. Matched instruction will be first && last and enter debug before first operation is retired.
• Deasserting tbljmp for trigger matches (similar to how all write enables are deassert in ID for trigger matches).

Above three changes are needed for E40S PC hardening logic, and are added to E40X for code consistency.

Not SEC clean due to different prefetch_ready which makes the instruction bus differ in SEC.

Signed-off-by: Oystein Knauserud Oystein.Knauserud@silabs.com