Update XIF interface

Created by: michael-platzer

Hi,

This PR updates the XIF interface definition, the LSU, and the WB stage to the changes in openhwgroup/core-v-xif@e65cc88 and openhwgroup/core-v-xif@6c257cd.

XIF memory requests are no longer aligned by the CPU. Instead, data and byte enable signals (wdata, rdata, and be) are assumed to be already aligned to the width of the memory bus (any required alignment and splitting must be performed by the coprocessor).

The XIF memory request's transaction attribute attr[1] (indicates whether the request is naturally aligned) is included in misaligned_access and thus made available to the PMA.

Question: I am unsure how to handle the other transaction attribute (attr[0], indicating whether the transaction was modified by the coprocessor) in CV32E40X. In the current PR this attribute is ignored. Does it need to be taken in account, and, if yes, what would be the consequence if it is set for a transaction?