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Unifying interrupt controllers; aligning cs registers syntax with cor…

Created by: Silabs-ArjanB

…e level

SEC clean for SMCLIC =0 and SMCLIC =1 (if clic_irq_priv_i = 2'b11)

Do NOT merge into the CV32E40S (will have a separate/similar PR).

Signed-off-by: Arjan Bink Arjan.Bink@silabs.com

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