Add XIF memory interface

Created by: michael-platzer

This PR adds the XIF memory interfaces (i.e., the memory request/response and the memory result interfaces) to CV32E40X.

The first commit replaces the size field in the XIF interface definitions with a byte enable mask as discussed here: https://github.com/openhwgroup/core-v-xif/issues/17

The second commit implements the base functionality required to handle memory requests by a coprocessor. Memory requests received via the XIF memory interface are converted into memory transactions. The aligner performs alignment for XIF memory data based on the lower bits of the address as usual, with the assumption that an XIF request always uses the entire width of the memory interface (i.e., is always 32 bits wide). Note that the byte enable mask received via the XIF interface is aligned as well. Split accesses are performed if required (as is done for internal memory transactions).

The third commit forwards MPU errors and bus errors resulting from XIF memory transactions to the coprocessor. MPU errors must be reported immediately via the XIF memory response interface, rather than being buffered as is done for internal transactions. This required some changes to the MPU, which has now the option to issue MPU errors via the new core_mpu_err_o port immediately.

As with previous patches related to the XIF interface, the new functionality is only enabled when X_EXT is 1. In particular, if X_EXT is 0, then the functionality of CV32E40X is not modified.

Acknowledgements: The changes in this PR have been inspired by earlier work by Kunal Dalal, Oana Lazar, Yu Xia, and Adomas Lebedys from the University of Southampton in the context of the AVA vector accelerator project, see: https://github.com/AI-Vector-Accelerator