Implement minimal CORE-V-XIF functionality

Created by: michael-platzer

This PR implements minimal functionality for the CORE-V-XIF eXtension interface by adding the required logic to the ID stage to drive the issue sub-interface, the FSM controller to drive the commit sub-interface, and the WB stage to receive results via the result sub-interface of the eXtension interface.

This minimal implementation is just enough to be usable at all for offloading instructions to a coprocessor and receiving results. It is neither complete nor error free. In particular, there are still following issues:

• Instruction IDs are not used, all instructions have ID 0.
• The controller commits all offloaded instructions regardless of any exceptions.
• Synchronous exceptions within the coprocessor indicated by the result interface are ignored (they only inhibit writeback of the result).
• Data hazards are ignored: If the result of an offloaded instruction is used by the subsequent instruction, then some random value is forwarded from the EX stage without waiting for the actual result (which only becomes available in the WB stage).

Despite these shortcomings, this implementation is already capable of offloading instructions to the vector coprocessor Vicuna.