Bugfix: Incorrect CSR stall for mret

Created by: silabs-oysteink

CSR stall logic did not take into account mret implicit writes when mret was in EX stage.

Removed dret from CSR stall logic as a dret kills the whole pipeline when it is in WB, and thus no hazard from that.

Signed-off-by: Oystein Knauserud Oystein.Knauserud@silabs.com