Misaligned load/store handled inside LSU

Created by: silabs-oysteink

Previously, the ID stage would update the id_ex_pipe for the second phase of a misaligned load/store while ID stage itself actually contained the next instruction. Now the load store unit does this itself. The ALU is no longer used for address calculation, and the alu_en may be set to 0 in a later change.

PR is SEC clean with one exception (see comments to diff).