Fix for i->o path, and ID stage assertions

Created by: silabs-oysteink

Suppressing *insn bits in the decoder using deassert_we caused a path from data_rvalid_i and to the instr interface, breaking timing.

Added a separate deassert signal for use when IF stage has PMA/PMP/bus_error, and uses this to deassert both write enables and the *_special bits in the decoder. This removes the timing path from the previous solution.

Also brought back in ID stage assertions. Work-in-progress to reenable them and/or move them to appropriate sva files.

Signed-off-by: Oystein Knauserud Oystein.Knauserud@silabs.com