Precursor to PC hardening, multi cycle jumps and branches

Created by: silabs-oysteink

Jumps (including mret) and branches are now treated as multi cycle / multi operation instructions.

These instructions will now spend two cycles in ID, EX and WB. A 'last_op' bit has been added to the id_ex_pipe and ex_wb_pipe, this bit will be low for the first cycle of jumps and branhces, and high for the second cycle and any other instructions. wb_valid will only go high for instructions with last_op=1.

• Passes ci_check.

• Not SEC clean. -- Non-taken branches gets one cycle extra penalty -- Jumps will get different stall conditions making it non-SEC

Signed-off-by: Oystein Knauserud Oystein.Knauserud@silabs.com