Timing fix
Created by: silabs-oivind
Combine cpuctrl_wr_in_wb and secureseed_wr_in_wb into xsecure_csr_wr_in_wb. Make xsecure_csr_wr_in_wb independent of control signals from FSM to ease timing.
SEC clean
Created by: silabs-oivind
Combine cpuctrl_wr_in_wb and secureseed_wr_in_wb into xsecure_csr_wr_in_wb. Make xsecure_csr_wr_in_wb independent of control signals from FSM to ease timing.
SEC clean
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