Merge requests · OpenHW Group / backup-20241120 / cv32e40p · GitLab

Issue #1027 correction.

!1029 · created Jul 19, 2024 by Eclipse Webmaster dev
Component:Doc
- Merged
- 1
updated Jul 24, 2024
merge dev into master

!1026 · created Jul 13, 2024 by Eclipse Webmaster
- Merged
- 1
updated Jul 13, 2024
core-v-docs changed to programs

!1025 · created Jul 11, 2024 by Eclipse Webmaster dev
Component:Doc
- Merged
- 1
updated Jul 11, 2024
All links updated to cv32e40p_v1.8.3 tag for the 3 target repos (core-v-docs, cv32e40p, core-v-verif).

!1024 · created Jul 11, 2024 by Eclipse Webmaster dev
Component:Doc
- Merged
- 1
updated Jul 11, 2024
User Manual final updates.

!1020 · created Jul 03, 2024 by Eclipse Webmaster dev
Component:Doc
- Merged
- 1
updated Jul 03, 2024
Up-to-date files for RISC-V ISA Formal Verification.

!1014 · created Jun 27, 2024 by Eclipse Webmaster dev
Component:Verif
- Merged
- 2
updated Jul 03, 2024
jasper SLEC script changes

!1003 · created Jun 12, 2024 by Eclipse Webmaster dev
Component:Tool-and-build Component:Verif
- Merged
- 24
- Approved
updated Jun 28, 2024
RISC-V ISA Formal Verification setup and script files for Siemens Questa Processor tool

!1008 · created Jun 20, 2024 by Eclipse Webmaster dev
Component:Verif
- Merged
- 2
updated Jun 21, 2024
RVFI - Correction corner case conflict on mstatus_fs upades when integer load followed by fpu instr

!998 · created Jun 06, 2024 by Eclipse Webmaster dev
Component:Verif
- Merged
- 2
updated Jun 06, 2024
Adding formal rule for coverage holes on controller

!997 · created Jun 06, 2024 by Eclipse Webmaster dev
Component:Tool-and-build Component:Verif
- Merged
- 2
updated Jun 06, 2024
merging dev to master after verifying LEC to v1

!996 · created Jun 05, 2024 by Eclipse Webmaster
- Merged
- 1
updated Jun 05, 2024
User Manual verification section update.

!992 · created May 30, 2024 by Eclipse Webmaster dev
Component:Doc
- Merged
- 1
updated Jun 03, 2024
Few lec scripts cleanup and improvements.

!991 · created May 30, 2024 by Eclipse Webmaster dev
Component:Tool-and-build Type:Enhancement
- Merged
- 2
updated Jun 03, 2024
Reverted PR #993.

!995 · created Jun 03, 2024 by Eclipse Webmaster dev
Component:Tool-and-build Component:Verif
- Merged
- 1
updated Jun 03, 2024
RISC-V ISA Formal Verification files for SiemensEDA OneSpin tool.

!993 · created May 30, 2024 by Eclipse Webmaster dev
Component:Tool-and-build Component:Verif
- Merged
- 4
- Approved
updated Jun 03, 2024
Code coverage holes formal analysis

!994 · created May 31, 2024 by Eclipse Webmaster dev
Component:Tool-and-build Component:Verif
- Merged
- 3
- Approved
updated May 31, 2024
Update pointer to v1.0.0 coverage reports

!989 · created May 24, 2024 by Mike Thompson dev
Component:Doc
- Merged
- 2
updated May 27, 2024
Fix #683

!687 · created Mar 23, 2022 by Eclipse Webmaster
Component:Verif
- Merged
- 25
updated May 16, 2024
Added HWloop CSRs save/restore

!987 · created Apr 26, 2024 by Eclipse Webmaster dev
Component:Doc
- Merged
- 1
updated Apr 26, 2024
Setting correct mstatus fs write mask when csrw to frm and correcting cv.beqimm & cv.bneimm printing in log file

!986 · created Apr 26, 2024 by Eclipse Webmaster dev
Component:Verif
- Merged
- 2
updated Apr 26, 2024

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