[fpga] Modify Perf. Counter for DSP Inference

Created by: ganoam

This commit modifies performance counter implementation to allow inference of DSP slices to absorb counter logic on FPGAs. By making use of the dedicated circuitry we are able to save both logic and flip-flop resources.

Summary of changes:

• Counter logic is moved to a new separate module
• The preprocessor variable TARGET_XILINX (automatically set by Bender) is used to include the required synthesis pragma.
• DSP Inferenceis supported for Xilinx FPGA devices featureing DSP48E1 slices or similar and for counter widths up to 48 bits. However, for widths of <= 32 bits only, the corresponding flip-flops can be absorbed into the DSP's output pipeline register.
• Therefore, a new top-level parameter WIDTH_MHPMCOUNTERS is introduced to control the width of the additional performance counters.
• The two primary counters mcycle and minstret are unaffected and remain at a width of 64 bits and are implemented in logic fabric.

Concrete savings: (Synthesis with 29 32-bit counters, target: Virtex-7)

                LUT     FF      DSP
 ----------------------------------
 baseline:      8951    3858    7
 opt:           7976    2917    36
 ----------------------------------
 Diff           -975    -941    +29
                -10.9%  -24.4%

Signed-off-by: ganoam gnoam@live.com