Fix for issue 325

Created by: davideschiavone

This should solve the issue #325 (closed)

I tried this on the core-v-verif , which needs some updates to be used with this version of the core.

For this reasons, I created a branch on the core-v-verif

https://github.com/openhwgroup/core-v-verif/tree/fix325_cv32e40p

This branch does not point to the right core, this should be done manually as I prefer that we do as following (in this order):

** @GTumbush tries this fix by:

• using the fix325_cv32e40p branch of core-v-verif by doing git checkout fix325_cv32e40p

• changing the core by using the core of this pull request. You can change the Makefile if you prefer, or adding a remote to that core, or simply replacing the core folder with a new fork of the core pointing to the right branch:

git clone git@github.com:davideschiavone/riscv.git
cd riscv
git checkout fix325 

Probably you need to rename to folder to cv32e40p

This is the output I got:

uvmt_cv32_tb.end_of_test: * Test Summary *
PPPPPPP    AAAAAA    SSSSSS    SSSSSS   EEEEEEEE  DDDDDDD     
PP    PP  AA    AA  SS    SS  SS    SS  EE        DD    DD    
PP    PP  AA    AA  SS        SS        EE        DD    DD    
PPPPPPP   AAAAAAAA   SSSSSS    SSSSSS   EEEEE     DD    DD    
PP        AA    AA        SS        SS  EE        DD    DD    
PP        AA    AA  SS    SS  SS    SS  EE        DD    DD    
PP        AA    AA   SSSSSS    SSSSSS   EEEEEEEE  DDDDDDD     
----------------------------------------------------------
             SIMULATION PASSED with WARNINGS              
----------------------------------------------------------

=N:[WriteMetrics] Writing coverage metrics...
=T:Simulation terminated by $finish at time 334081500 (/tools/Metrics/dsim/20200316.6.0/uvm-1.2/src/base/uvm_root.svh:517);
Run directory: /data/davide/GitHubRepos/openhwgroup/core-v-verif/master/cv32/sim/uvmt_cv32/dsim_results/riscv_ebreak_test_0

• If you confirm so and if I didn't create any more regressions, we merge this PR, then I update the core-v-verif pointing to the right core and create another related PR

Do you agree @MikeOpenHWGroup , @GTumbush ?