Add Verilator model

Created by: gmarkall

Further to discussion with Davide Rossi at ORConf, this pull request adds a Verilator model that can be used for cycle-accurate modelling of the RI5CY core. A very simple RAM is also added (a modified version of one copied from Pulpino).

This is the same model that was presented along with performance and GCC regression test results at ORConf ( http://gmarkall.github.io/tutorials/orconf-2017/#1 ) and is used in the toolchain we have been working with ( https://github.com/embecosm/riscv-toolchain/tree/orconf#orconf-risc-v-toolchain-quick-start ).

A testbench for the model is included, which demonstrates how the model can be driven from C++, in particular:

• Instantiating the model
• Writing data to memory (a short program)
• Resetting the CPU
• Running the CPU
• Using the debug unit to halt, set traps on exceptions, single-step, and resume.

The testbench only provides a sample of running a very simple sequence of instructions - for running (and debugging) whole programs on the model through GDB, the Toolchain Quick-start Guide explains the steps to follow.

Feedback is very welcome - this is our first PR to the project, so any guidance would be much appreciated!