Pull request from OpenHW Group

Hi, this is Mike Thompson from the OpenHW Group. We are doing some preliminary work to prepare for the CORE-V CV32 project, which will be based on the RI5CY core. I've done some work which I think may be of benefit to RI5CY and hence this pull-request.

The big changes in this PR:

1. Add Makefile rules for the Metrics SystemVerilog simulator dsim. These rules will not affect anyone not using dsim.
2. Separate the RTL and TB source files. This involved significant changes to Makefile variables and also moving one file from the tb/core directory to the rtl directory.
3. Removed the rvc.S testcase as it does not compile (we have created an issue to ensure it does not get forgotten).

One minor issue - my updates to README.md are relevant to my fork only - you probably don't want to merge that.