[RISCV] Support for CoreV bit manipulation intrinsics

Created by: melonedo

This PR implements an internal interface and the necessary mechanism for decoding the parameter of a bit manipulation builtin.

Note that for a builtin __builtin_riscv_cv_bitmanip_bclr(a, range), the generated instruction would be cv.bclr rD, rs1, range[9:5], range[4:0], that is, the upper 5 bits come after the lower 5 bits, as pointed out in https://github.com/openhwgroup/corev-gcc/issues/32.