[RISCV] Support encoding SIMD instructions (!27) · Merge requests · OpenHW Group / backup-20241120 / corev-llvm-project

Eclipse Webmaster requested to merge github/fork/melonedo/simd-encoding-pr into development Jan 19, 2023

Created by: melonedo

Support encoding cv32e40p SIMD instructions. Spec: https://github.com/openhwgroup/cv32e40p/blob/2a12206f84f53d4538d3876a1da367664c70e501/docs/source/instruction_set_extensions.rst.

Discussion: In the SIMD ALU Operations section of the spec, instructions cv.minu/maxu/srl/sra/sll.h/b are zero-extended, but support negative immediates in gdb (as in cv-maxu-sci-b-pass.s). I made them all signed like other instructions, is it desirable?

[RISCV] Support encoding SIMD instructions

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