Add branching immediate instructions, and GAS tests

Created by: NBruschi

gas/Changelog.COREV:

* config/tc-riscv.c (riscv_multi_subset_supports): Add immediate
branching instruction class.
(validate_riscv_insn, riscv_ip): Rename macro
ENCODE_CV_ALU_UIMM5 -> ENCODE_CV_UIMM5.
(validate_riscv_insn, riscv_ip): Add immediate branching
operand and modify PC-relative offset operand.
* doc/c-riscv.texi: Add details on CORE-V immediate
branching ops ISA options.

gas/testsuite/Changelog.COREV:

* gas/riscv/cv-bi-beqimm.d: Add immediate branching test.
* gas/riscv/cv-bi-beqimm.s: Likewise.
* gas/riscv/cv-bi-bneimm.d: Likewise.
* gas/riscv/cv-bi-bneimm.s: Likewise.
* gas/riscv/cv-bi-fail-march.d: Likewise.
* gas/riscv/cv-bi-fail-march.l: Likewise.
* gas/riscv/cv-bi-fail-march.s: Likewise.
* gas/riscv/cv-bi-fail-operand-01.d: Likewise.
* gas/riscv/cv-bi-fail-operand-01.l: Likewise.
* gas/riscv/cv-bi-fail-operand-01.s: Likewise.
* gas/riscv/cv-bi-fail-operand-02.d: Likewise.
* gas/riscv/cv-bi-fail-operand-02.l: Likewise.
* gas/riscv/cv-bi-fail-operand-02.s: Likewise.
* gas/riscv/cv-bi-fail-operand-03.d: Likewise.
* gas/riscv/cv-bi-fail-operand-03.l: Likewise.
* gas/riscv/cv-bi-fail-operand-03.s: Likewise.
* gas/riscv/cv-bi-fail-operand-04.d: Likewise.
* gas/riscv/cv-bi-fail-operand-04.l: Likewise.
* gas/riscv/cv-bi-fail-operand-04.s: Likewise.
* gas/riscv/cv-bi-march-rv32i-xcorev.d: Likewise.
* gas/riscv/cv-bi-march-rv32i-xcorev.s: Likewise.

include/Changelog.COREV:

* opcode/riscv-opc.h: Add immediate branching matches and
masks.
* opcode/riscv.h (riscv_insn_class, EXTRACT_CV_BI_IMM5):
Add immediate branching class and macros for 5-bit signed
immediate.
(ENCODE_CV_ALU_UIMM5): Rename macro as ENCODE_CV_UIMM5.
(RV_IMM_SIGN_N): Add macro for general sign extraction.

ld/testsuite/Changelog.COREV:

* ld-riscv-elf/cv-bi-beqimm.d: Add new test.
* ld-riscv-elf/cv-bi-beqimm.s: Likewise.
* ld-riscv-elf/cv-bi-bneimm.d: Likewise.
* ld-riscv-elf/cv-bi-bneimm.s: Likewise.
* ld-riscv-elf/ld-riscv-elf.exp: Add CORE-V immediate
branching tests.

opcodes/Changelog.COREV:

* riscv-dis.c (print_insn_args): Add immediate branching
operand.
* riscv-opc.c (riscv_opcodes): Add immediate branching
opcodes.

Signed-off-by: Nazareno Bruschi nazareno.bruschi@embecosm.com