add the Verilab SVLIB to cv32e40x

Created by: strichmo

To provide useful common utilities (including regexp parsing, extended file operators, time functions, etc.) the Open Source Verilab SVLIB library will be cloned and compiled into all core-v-verif simulations.

The SVLIB itself is licensed under Apache 2.0, however no source code is included in the environment. The SVLIB is hosted at a bitbucket site and is cloned as other 3rd party libraries (e.g. riscv-dv and Spike)

This has been tested with dsim, Xcelium, and Questa. The Riviera and VCS makefiles are updated, but untested.

A common makefile target is added to enable rebuilding the SVLIB DPI shared library (make svlib). A 64-bit Linux shared library is checked into this PR which should work for any Linux users of core-v-verif.