Integrate disassembler/decoder into ISA coverage model

Created by: silabs-robin

This PR integrates a disassembler/decoder into the isa coverage agent in accordance with https://github.com/openhwgroup/core-v-verif/issues/487. It makes use of a few source files from riscv-isa-sim in order to extract fields and names of instruction word binaries. The ad-hoc decoder in uvma_isacov_mon is replaced by this integrated disassembler.

Usage:

1. In "uvme_cv32e40x_cfg.sv", isacov_cfg.enabled should be == 1.
2. In "cv32e40x/sim/uvmt", run make dpi_dasm
3. Run any make test ... and append these variables to the command:
   • USER_COMPILE_FLAGS='+define+DPI_DASM'
   • USER_RUN_FLAGS='-sv_lib $(DPI_DASM_PKG)/libdpi_dasm.so'
4. (One can read more in lib/dpi_dasm/README.md and lib/uvm_agents/uvma_isacov/README.md)

Testing: I have tested this, but with the current unavailability of the ISS the testing is not 100%. In any case, the default behavior should be that the disassembler and uvma_isacov are not enabled and the tests themselves should not be affected (passive agent). Without the "USER_" flags above, normal behavior is untouched as far as I could tell while testing different combinations of make args.

NB: RVC (compressed instructions) is not yet implemented because RVFI (or equivalent) first needs to replace the tracer so that non de-compressed instruction binaries can be fed to the disassembler and coverage model. But the disassembler does support "C" and much more, and we have tested this functionality outside of the integration.