Updated Riscv-dv to latest hash

Created by: silabs-hfegran

Summary of changes:

    - Removed jump to init_machine_mode (function location inlined
      by Google, no longer needed).

    - Reverted previous mret->ret change to init_machine_mode
      generator function to avoid an infinite loop.

    - Changed setup_mmode_reg to not enable MIE bit.
      This is instead done by mret at the end of code section
      by copying MPIE->MIE. (cf. riscv priv. spec.)
      This prevents an infinite loop if an interrupt request is
      present prior to init_machine_mode completion.

    - Updated common interrupt handler jump for increased robustness
      with large programs. (Ports over change from RISCV-DV
      upstream).

    - Added empty custom csr definitions for compatibility with
      latest Riscv-dv.

Signed-off-by: Henrik Fegran Henrik.Fegran@silabs.com