interrupt testbench updates to work with new simplified interrupt controller
Created by: strichmo
Rewrite all interrupts and "deferint modeling" code with the ISS to work with the new interrupt controller introduced in this PR:
https://github.com/openhwgroup/cv32e40p/pull/511
These changes should regress clean against all current cv32e40p directed and random interrupt tests.
Note that the above RTL PR update to the git hash in core-v-verif must occur in conjunction with merging this PR.