CV32E40P fix for mem stress scenario with compressed instructions

Created by: XavierAubert

The following code generation command would fail (see attached file for error message);

make gen_corev-dv TEST=corev_rand_illegal_instr_test CV_CORE=cv32e40p CFG=pulp_fpu_zfinx_1cyclat TEST_CFG_FILE=floating_pt_zfinx_instr_en,disable_all_trn_logs SIMULATOR=vsim SEED=1248233755

This was due to memory stress streams randomly reserving all allowed registers for compressed instructions (S0 to A5)

The fix consists in checking the number of S0:A5 registers that have been already reserved before randomization, and making sure that there are less registers taken in that range.

mem_stress_with_compress_failure.log