CV32E40Pv2 Verification update Week 16 PR
Created by: dd-BeeNee
This Pull Request contains the work from last week, mainly updates to match RTL tag v1.7.2, as well as enhancements to improve function/code coverages. Contributors are @dd-baoshan
, @dd-BeeNee
, @pascalgouedo
, @YoannPruvost.
Updated code coverage to be in sync with RTL tag v1.7.2, by @dd-BeeNee
:
Enhanced function coverage, by @dd-baoshan
:
-
@https
://github.com/XavierAubert/core-v-verif/pull/230 -
@https
://github.com/XavierAubert/core-v-verif/pull/227 -
@https
://github.com/XavierAubert/core-v-verif/pull/224 -
@https
://github.com/XavierAubert/core-v-verif/pull/221
Updated stream generator to generate legal imm6 value for SIMD instr:
Updated test settings to improve code coverage, by @pascalgouedo
and assertion correspond to T-head FDIV/FSQRT behavior when waiting from WFI to sleep
-
@https
://github.com/XavierAubert/core-v-verif/pull/226 -
@https
://github.com/XavierAubert/core-v-verif/pull/222 -
@https
://github.com/XavierAubert/core-v-verif/pull/219
Updated Imperas DV wrap to handle mhpmevents csr, by @YoannPruvost