[Xcelium support] Bugfix uvm sysverilog compliant (!2365) · Merge requests · OpenHW Group / backup-20241120 / core-v-verif

Eclipse Webmaster requested to merge github/fork/boschglobal/bugfix/uvm_sysverilog_compliant into master Feb 13, 2024

Created by: CoralieAllioux

Those minor fixes are suggested in the context of supporting Cadence Xcelium simulator for cva6 verification. Those modifications allows Xcelium to compile and does not impact VCS usage.

This has been check with VCS 2021.09.

[Xcelium support] Bugfix uvm sysverilog compliant

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