Skip to content

CV32E40Pv2 Verification update

Created by: XavierAubert

Below are backlog updates for the last two months. I tried to organize everything to a more readable way, by topic, and to bring focus on important changes.

  • Floating Point Instructions (Coverage, tests and fixes)

  • A general rework of a dismissed PR (#1990) was added back into the environment (for details, see XavierAubert#95)

  • After this rework, various updates have been made to improve coverage, fixes, analyzing redundant code (commits 03a57e18, 3dbad3a8)

  • By analyzing coverage, holes have been found and filled with new tests. First, mstatus.fs is covered by this new test (Added in XavierAubert#97, further improved/fixed in XavierAubert#109)

  • Illegal Instruction added for RV32FC XavierAubert#123

  • HWLoop Instructions

  • A vast majority of updates targetted on HWLoop are back-and-forth debugging to make sure all specific event and scenarios are correctly detected and general coverage improvements :

    • XavierAubert#96
    • XavierAubert#108
    • XavierAubert#112
    • XavierAubert#116
    • XavierAubert#119
    • 61b536ff from XavierAubert#120
    • XavierAubert#122
    • 19edee3f from XavierAubert#128
    • d3e7cad7 from XavierAubert#130
    • XavierAubert#138
  • Interrupt & Debug

  • Fix for Load and Stores instructions in debug program, and added PULP instructions generation inside debug program XavierAubert#103

  • Random FP instructions streams added with interrupt & debug options enabled (commit 05d82275 from XavierAubert#124, frequency of debug request reduced afterwards for some tests in 069dc310 from XavierAubert#126)

  • Flow/Regression updates and fixes

  • A long-run issue inside our CI environment regarding UCDB merging and performance issues have been addressed during the past couple of months, experimenting a lot with Siemens tools options and tests timeout and their organization inside the regress lists (See XavierAubert#100, XavierAubert#102, XavierAubert#107, c5cdd274, XavierAubert#125, ee0a2c2e, 93117b03)

  • A new option has been added to regression generation, to allow a test to have a fixed seed (XavierAubert#127)

  • Testbench updates and fixes

  • Temporary workaround for GNU GCC issue https://github.com/openhwgroup/corev-gcc/issues/36 in XavierAubert#113 and XavierAubert#129

  • Toggle coverage collection removed 2f5ac427

  • corev-dv generation fix regarding avail_regs that was causing issues (commit 13f5a602 from XavierAubert#98 and XavierAubert#99

  • commit 44647b9a inside PR XavierAubert#98 also addresses the following issue #2286 (closed)

  • Prevent load & store from corrupting main code 56ba26f6 & d76e6b68 from XavierAubert#132

  • Verification planning updates, tests additions, regression lists updates

  • Additions to FPU Register / FP Instr test plan XavierAubert#75

  • Removed the two cluster configurations from what is verified XavierAubert#104

  • Added more debug tests for XPULP instructions, commit 36d1b29c in XavierAubert#111

  • Added a new test to improve decoder coverage for CUSTOM opcodes illegal instructions (XavierAubert#131, XavierAubert#135, XavierAubert#136)

  • Added new hwloop debug test 4361141d in XavierAubert#132

  • Various test names & test options changes XavierAubert#115, XavierAubert#118

Merge request reports

Loading