SV32-DV-Plan Execution

Created by: Ammar-10xe

Hello everyone,

This PR is adding a comprehensive set of self-checking assembly tests to execute the SV32 testplan for the architectural verification of SV32 MMU of the step 1 CVA6 configuration (CV32A6X). There are 60 tests in total, that are listed in riscv-arch-test-mmu YAML file.

Here's an overview of the different categories covered by these tests

Test Features	Test Description
SATP	Examines various common cases related to SATP, including access permissions at different privilege levels, the modes field, and ASIDLEN settings.
PMP Permissions	Assesses PMP permissions on both physical addresses and PTEs.
PTE Validity and Permissions	Evaluates the Read/Write/Execute (RWX) permissions of PTEs with the valid bit set to 0, including reserved encodings at level 1 and level 0 PTEs, and non-leaf PTEs for level 0 in both user and supervisor modes.
Access on Supervisor and User Pages	Tests access permissions for Supervisor and User mode pages in both supervisor and user privilege levels for both level 0 and level 1 PTEs.
Executable Page Readability	Checks the behavior of readable executable pages with different s/mstatus.MXR settings.
RWX access on U mode pages in S mode	Examines RWX access of User mode pages in Supervisor mode with different s/mstatus.SUM settings.
Access and Dirty Bit Implementation	Evaluates the implementation and effects of the access and dirty bits (A and D) on page fault exceptions.
Misaligned Superpage	Investigates page faults for misaligned superpages at level 1 PTEs in both user and supervisor modes.