RISCV CVA6 32-bit CSR Access Verification PR-1 (!2105) · Merge requests · OpenHW Group / backup-20241120 / core-v-verif

Eclipse Webmaster requested to merge github/fork/spidugu444/cv32a6_csr_access_pr into cva6/dev Aug 06, 2023

Created by: spidugu444

Hi,

please find the PR for CVA6 32-bit CSR Access Verification.

Highlights:

1. Added Yaml files for CVA6 32-bit CSRs, which has been categorized into supervisor mode read-write CSRs, Machine mode read-write CSRs and read-only CSRs.
2. Added Test files for CVA6 32-bit CSRs, which has been categorized into supervisor mode read-write CSRs, Machine mode read-write CSRs, read-only CSRs and counter CSRs. each CSR has been verified on all privileged modes (Supervisor, Machine and User modes).
3. Added CVA6 32-bit CSR access failing test cases.

please let me know if any changes are needed.

Thanks

RISCV CVA6 32-bit CSR Access Verification PR-1

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