[SPIKE] sim.cc: do not yield load reservation on single core (!2103) · Merge requests · OpenHW Group / backup-20241120 / core-v-verif

Created by: ASintzoff

to have same behaviour on spike and on RTL with one core, do not yield load reservation at the end of each block of INTERLEAVE steps

Signed-off-by: André Sintzoff andre.sintzoff@thalesgroup.com

[SPIKE] sim.cc: do not yield load reservation on single core