RISCV CVA6 32-bit CSR Access Verification PR

Created by: spidugu444

Hi, @JeanRochCoulon , please find the PR for CVA6 32-bit CSR Access Verification.

Highlights:

1. Added Yaml files for CVA6 32-bit CSRs, which has been categorized into supervisor mode read-write CSRs, Machine mode read-write CSRs and read-only CSRs.
2. Added Test files for CVA6 32-bit CSRs, which has been categorized into supervisor mode read-write CSRs, Machine mode read-write CSRs, read-only CSRs and counter CSRs. each CSR has been verified on all privileged modes (Supervisor, Machine and User modes).
3. Added CVA6 32-bit CSR access failing test cases.
4. Added updated DV plan for CVA6 32-bit CSR Access Verification. 5.Since we are testing the behavior of the counter CSRs, iteration zero has been added to the test list for the counter CSRs (CYCLE and INSTRET), as it generates a different value on the spike and RTL ends.

please let me know if any changes are needed.

Thanks