ISACOV - Add Missing Macro

Created by: silabs-robin

Current "master" doesn't compile.

This PR adds a missing macro so that 40s can make comp without error.

Test status:

• ci_check - Mostly passes
  • Failure on corev_rand_interrupt, GPR mismatch.
    • (I don't remember if this used to be a known issue.)
    • (I don't know if our current up-to-date iss is backwards-compatible to that date.)
  • Note: Ran with export CV_SW_MARCH=rv32im_zicsr_zca_zifencei

Notes:

• This relates to the new cva6/dev -> master PR: https://github.com/openhwgroup/core-v-verif/pull/1887
• The problem was introduced on the previous cva6/dev -> master PR: https://github.com/openhwgroup/core-v-verif/pull/1512
• The problem is that SC (store conditional) rd return values can be 0 or 1, but the macro for that toggle coverage was deleted so Xcelium refused to compile when using an undefined macro.

Spec: