cv32e40p riscof flow updates for failures and action items from initial PR

Created by: dd-vaibhavjain

In this PR mainly 3 things are done:

1.) Modify default riscof config.ini to target cv32e40p v1 runs and added a new config file : cv32e40p_v2.ini along with 2 new files -> cv32e40p_v2_isa.yaml and cv32e40p_v2_platform.yaml to target cv32e40pv2. This is done as part of previous action items to support multiple configs for the core and here with all the files in place, the flow is up and able to generate run test suite and generate reports for different configs.

2.) Removed the FIXME/workarounds in signature writer and now using actual begin_signature/end_signature symbol addresses from each test to dump the signature. For this now created a fixed location in linker file and use the User macros in riscof env model_test.h to write these locations with signature begin/end symbol addresses, and also updated the tb uvm test function for the same.

3.) Debug all the priviledge mode failures and found and fixed some missing TB defines based on core implementation specific things for exceptions and related CSRs. Also needed some update to sail ref model commands based on yaml.

This is done along with small minor fixes and improvements in vsim.mk , uvmt test and py plugins for debug and cleanup.