Adding RISCOF riscv-arch-test suite simulation support for cv32e40p and related flow updates

Created by: dd-vaibhavjain

Purpose of this PR is to add support for running RISCOF riscv-arch-test suite within core-v-verif environment.

The files added for the flow follow the riscof documentation at : https://riscof.readthedocs.io/en/stable/

New Files Added:

1. RISCOF setup related files are added under a new dir: core-v-verif/cv32e40p/sim/riscof/

• config.ini -> config file for riscof
• cv32e40p/ -> directory with required cv32e40p DUT intput files for ricof
• sail_cSim/ -> directory with required sail reference model input files for riscof
• README.md -> readme for this riscof setup explaining riscof run steps and requirements
• Makefile -> this is same as the makefile in core-v-verif/cv32e40p/sim/uvmt

2. new uvm test for riscof: core-v-verif/cv32e40p/tests/uvmt/compliance-tests/uvmt_cv32e40p_riscof_firmware_test.sv -> contains riscof related test configs and signature writer function

3. new make file for riscof flow support: core-v-verif/mk/riscof.mk -> contains all new variables and targets for riscof in one place

4. Other major file updates: core-v-verif/mk/uvmt/vsim.mk , xrun.mk, vcs.mk, uvmt.mk -> to add new riscof dut sim targets for different simulators . Updates are strictly added as new block of targets for riscof while keeping all existing code as such.

• The directory structure chosen in this way to avoid disrupting existing setup and have good distinction for riscof but still be able to make use if needed the exisiting bench's debugging and other uvm infrastructure
• the riscof setup files are created using initial templates provided by the riscof package and added with cv32e40p related commands
• signature writer is added as a function inside the uvmt_cv32e40p_riscof_firmware_test.sv rather than creating a new class of signature writer, as it seemed only relevant in this context of riscof and not something which has relevance for reusability
• signature writer has a FIXME at the moment. As this has some hardcoded addresses in line with linker file and some dependency on current data section of memory. But may need a way to parse the hex file and find the start and end of signature addresses to keep it generic and independent of linker file but this may have a performance penality to consider.
• more riscof config files and dut targets with different isa/platform values can be added but at the moment only 1 config is added to run with all possible standand extentions for cv32e40p and available in the test suite RV32IMFCZicsr_Zifencei.

The setup and flow works with vsim and xrun and a riscof report is able to generate at the end with some failures.