Add optional code coverage collection for DSIM

Hi @aimeepsutton. I have made a couple of simple updates to dsim.mk and have added a code coverage scope specification file to enable code coverage for DSIM. Alas, the latest version of dsim on the IBM VM does not support the code coverage command line arguments so I cannot test it. I got these args from the 20200720.0.0 version of the DSIM user manual.

The goal of this update is to enable code coverage of the cv32e40p core, including all levels beneath it, excluding the testbench and UVM environment. The make command is:

$ make sanity CCOV=1

and the resultant dsim command generated is:

dsim \
	-timescale 1ns/1ps  -top uvmt_cv32_tb \
	+incdir+/tools/Metrics/dsim/20200316.10.0/uvm-1.2/src /tools/Metrics/dsim/20200316.10.0/uvm-1.2/src/uvm_pkg.sv \
	 \
	"+define+ISS+CV32E40P_TRACE_EXECUTION" -code-cov block -code-cov-scope-specs /data/mike/GitHubRepos/openhwgroup/core-v-verif/code_cov/cv32/sim/uvmt_cv32/../tools/dsim/ccov_scopes.txt \
	+incdir+/data/mike/GitHubRepos/openhwgroup/core-v-verif/code_cov/cv32/sim/uvmt_cv32/../../../cv32/env/uvme_cv32 \
	+incdir+/data/mike/GitHubRepos/openhwgroup/core-v-verif/code_cov/cv32/sim/uvmt_cv32/../../../cv32/tb/uvmt_cv32 \
	-f /data/mike/GitHubRepos/openhwgroup/core-v-verif/code_cov/cv32/sim/uvmt_cv32/../../../core-v-cores/cv32e40p/cv32e40p_manifest.flist \
	-f /data/mike/GitHubRepos/openhwgroup/core-v-verif/code_cov/cv32/sim/uvmt_cv32/../../../cv32/tb/uvmt_cv32/uvmt_cv32.flist -f /data/mike/GitHubRepos/openhwgroup/core-v-verif/code_cov/cv32/sim/uvmt_cv32/../../../cv32/tb/uvmt_cv32/imperas_iss.flist \
	-work /data/mike/GitHubRepos/openhwgroup/core-v-verif/code_cov/cv32/sim/uvmt_cv32/dsim_results/dsim_work \
	+ \
	-genimage dsim.out

Signed-off-by: Mike Thompson mike@openhwgroup.org