MMU test plan for SV32 address translation scheme
Created by: Abdulwadoodd
Hi All,
This PR adds the Architecture test plan of the Virtual Memory - SV32 address translation scheme - for the verification of MMU of CVA6. MMU DV plan is one of the tasks assigned to 10xEngineers
from Step-1 Verification plan of the RISC-V CV32A6 v5.0.0
project.
Let me know if any changes are required.
Thanks,