Add support for E40X core simulation using Verilator/Questa Vsim

Created by: leemango1998

This PR is to set up the "core" testbench for E40X core. Related issues could be #1777 (closed), #1259 (closed).

The major modifications include:

1. cv32e40x/sim/core/Makefile: Some redefinition of variables. Remove redundant variable that have the same function(e.g., CUSTOM with TEST_PROGRAM_PATH, CUSTOM_PROG with TEST).

2. cv32e40x/tb/core/cv32e40x_tb_wrapper.sv: Correct the instance of cv32e40x core.

3. cv32e40x/tb/core/mm_ram.sv: Remap the virtual peripheral registers according to corev_uvmt.h.

4. cv32e40x/sim/core/readme.md: Update the usage of makefile commands.

Only verilator 5.008 and vsim 2021 were tested. For verilator, try make veri-test TEST=hello-world in cv32e40x/sim/core/ path to simualte the hello-word program. For vsim, try make questa-custom TEST=hello-world instead.