Add new mechanism of the end of test for generated tests

Created by: AyoubJalali

Hello, I add in the cva6_asm_program_gen.sv file, the gen_test_done function to implement the new end of test mechanism, so to use it you should add in the cmd line : --sim_opts="+uvm_set_inst_override=riscv_asm_program_gen,cva6_asm_program_gen_c,'uvm_test_top.asm_gen'" to override the original RISCV-DV class with the new one.