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Debug asserts

Created by: silabs-mateilga

Debug assertion set is completed and ready to merge. The assertion set has been updated to latest spec, and several asserts have been rewritten to reduce complexity, encompass more of the RTL and improve time to converge. The PR includes updated assertion set, updated Vplan with link to coverage, and a big upgrade to the helper functions in rvfi_instr_if.

Note that trigger asserts have been separated out in to it's own assertion set, and has been deleted from this file.

There are a few TODO's left:

  • Support logic detecting exception trigger matches from trigger 0 is a placeholder for a more complete support logic that will come from the trigger assertion set work
  • A few assertions that have been split up are left in, marked as redundant. They are left in to facilitate an experiment to see if they will converge faster when the "children" of the split has been proven.

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