Clean up handling of ISA variants when disassembling RTL sim output.

Created by: zchamski

This PR streamlines the handling of ISA variants when post-processing RTL simulationt output. In particular, it should now seamlessly handle HW configurations with non-standard names (broken since commit c13b99ac).

Root cause

In order to correctly disassemble the instruction trace, the RISC-V disassembler dasm needs to know the exact ISA variant used during the simulation (the same encodings can have distinct interpretations depending on XLEN.) However, the guessing approach implemented in commit c13b99ac did not handle arbitrary target configuration names such as those used for HW config tests.

Root fix

Use the same information passing mechanism as for spike simulations: the ISA variant is available in DV parameter <variant> and its value should be passed to the simulation Makefile upon invoking make for all RTL simulation targets.

Change log

• cva6/sim/Makefile (target_isa): Remove. (vcs-testharness): Use $(variant) instead of $(target_isa). (veri-testharness): Ditto. (vcs-uvm): Ditto.
• cva6/sim/cva6.yaml (veri-testharness): Provide ISA variant to simulation wrapper. (vcs-testharness): Ditto. (vcs-gate): Ditto. (vcs-uvm): Ditto.

Signed-off-by: Zbigniew Chamski zbigniew.chamski@thalesgroup.com